Intel Core 2 Extreme QX9300 BX80562QX9300 User Manual

Datasheet

59

D[63:0]#

Input/

Output

D[63:0]# (Data) are the data signals. These signals provide a 
64-bit data path between the FSB agents, and must connect the 
appropriate pins on both agents. The data driver asserts DRDY# to 
indicate a valid data transfer.
D[63:0]# are quad-pumped signals and will thus be driven four 
times in a common clock period. D[63:0]# are latched off the 
falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group 
of 16 data signals correspond to a pair of one DSTBP# and one 
DSTBN#. The following table shows the grouping of data signals to 
data strobes and DINV#. 

Furthermore, the DINV# pins determine the polarity of the data 
signals. Each group of 16 data signals corresponds to one DINV# 
signal. When the DINV# signal is active, the corresponding data 
group is inverted and therefore sampled active high. 

DBR#

Output

DBR# (Data Bus Reset) is used only in processor systems where 
no debug port is implemented on the system board. DBR# is used 
by a debug port interposer so that an in-target probe can drive 
system reset. If a debug port is implemented in the system, DBR# 
is a no connect in the system. DBR# is not a processor signal.

DBSY#

Input/

Output

DBSY# (Data Bus Busy) is asserted by the agent responsible for 
driving data on the FSB to indicate that the data bus is in use. The 
data bus is released after DBSY# is deasserted. This signal must 
connect the appropriate pins on both FSB agents.

DEFER#

Input

DEFER# is asserted by an agent to indicate that a transaction 
cannot be ensured in-order completion. Assertion of DEFER# is 
normally the responsibility of the addressed memory or input/
output agent. This signal must connect the appropriate pins of both 
FSB agents.

D[15:0]#

0

0

D[31:16]#

1

1

D[47:32]#

2

2

D[63:48]#

3

3