Intel i5-4300Y CL8064701558601 Data Sheet

register. Customers choosing to change the value of this register can do it by

changing it in the BIOS. For experiments, this register can be modified in real time if

BIOS does not lock the IMC registers.

During power-up, CKE is the only input to the SDRAM that has its level recognized

(other than the DDR3L/DDR3L-RS reset pin) once power is applied. It must be driven

LOW by the DDR controller to make sure the SDRAM components float DQ and DQS

during power-up. CKE signals remain LOW (while any reset is active) until the BIOS

writes to a configuration register. Using this method, CKE is ensured to remain

inactive for much longer than the specified 200 micro-seconds after power and clocks

to SDRAM devices are stable.

During S0 idle state, system memory may be conditionally placed into self-refresh

 for more details on conditional self-

refresh with Intel HD Graphics enabled.

When entering the S3 – Suspend-to-RAM (STR) state or S0 conditional self-refresh,

the processor core flushes pending cycles and then enters SDRAM ranks that are not

used by Intel graphics memory into self-refresh. The CKE signals remain LOW so the

SDRAM devices perform self-refresh.

The target behavior is to enter self-refresh for package C3 or deeper power states as

long as there are no memory requests to service. The target usage is shown in the

following table.

C0, C1, C1E

Dynamic memory rank power-down based on

idle conditions.

Dynamic memory rank power-down based on

idle conditions.

C3, C6, C7

or deeper

If the processor graphics engine is idle and

there are no pending display requests, then

enter self-refresh. Otherwise, use dynamic

memory rank power-down based on idle

conditions.

If there are no memory requests, then enter

self-refresh. Otherwise, use dynamic memory

rank power-down based on idle conditions.

S3

Self-Refresh Mode

Self-Refresh Mode

S4

Memory power-down (contents lost)

Memory power-down (contents lost)

Dynamic power-down of memory is employed during normal operation. Based on idle

conditions, a given memory rank may be powered down. The IMC implements

aggressive CKE control to dynamically put the DRAM devices in a power-down state.

The processor core controller can be configured to put the devices in active power-

down (CKE de-assertion with open pages) or pre-charge power-down (CKE de-

assertion with all pages closed). Pre-charge power-down provides greater power

savings, but has a bigger performance impact since all pages will first be closed before

putting the devices in power-down mode.

Mobile 4th Generation Intel

®

 Core

™

 Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and Mobile Intel

®

 Celeron

®

Processor Family

July 2014

Datasheet – Volume 1 of 2

Order No.: 329001-007

55