Intel i5-4300Y CL8064701558601 Data Sheet

If dynamic power-down is enabled, all ranks are powered up before doing a refresh

cycle and all ranks are powered down at the end of refresh.

Unused signals should be disabled to save power and reduce electromagnetic

interference. This includes all signals associated with an unused memory channel.

Clocks, CKE, ODE, and CS signals are controlled per DIMM rank and will be powered

down for unused ranks.

The I/O buffer for an unused signal should be tri-stated (output driver disabled), the

input receiver (differential sense-amp) should be disabled, and any DLL circuitry

related ONLY to unused signals should be disabled. The input path must be gated to

prevent spurious results due to noise on the unused signals (typically handled

automatically when input receiver is disabled).

The DDR I/O of the processor supports Electrical Power Gating (DDR-EPG) while the

processor is at C3 or deeper power state.

In C3 or deeper power state, the processor internally gates V

DDQ

 for the majority of

the logic to reduce idle power while keeping all critical DDR pins such as CKE and

VREF in the appropriate state.

In C7 or deeper power state, the processor internally gates Vcc

ST

 for all non-critical

state to reduce idle power.

In S3 or C-state transitions, the DDR does not go through training mode and will

restore the previous training information.

Intel Rapid Memory Power Management (Intel RMPM) conditionally places memory

into self-refresh when the processor is in package C3 or deeper power state to allow

the system to remain in the lower power states longer for memory not reserved for

graphics memory. Intel RMPM functionality depends on graphics/display state

(relevant only when processor graphics is being used), as well as memory traffic

patterns generated by other connected I/O devices.

Render C-state (RC6) is a technique designed to optimize the average power to the

graphics render engine during times of idleness. RC6 is entered when the graphics

render engine, blitter engine, and the video engine have no workload being currently

worked on and no outstanding graphics memory transactions. When the idleness

condition is met, the processor graphics will program the graphics render engine

internal power rail into a low voltage state.

Mobile 4th Generation Intel

®

 Core

™

 Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and Mobile Intel

®

 Celeron

®

Processor Family

Datasheet – Volume 1 of 2

July 2014

56

Order No.: 329001-007