Intel 2955U CL8064701523900 Data Sheet

Product codes
CL8064701523900
Page of 123
Figure 9.
Processor Package and Core C-States
One or more cores or GT executing instructions
All cores and GT in C3 or deeper, L3 may be flushed and turned off, memory in self refresh, some Uncore 
clocks stopped, some Uncore voltages reduced
All cores and GT in C6 or deeper, L3 may be flushed and turned off, memory in self refresh, all Uncore 
clocks stopped, some Uncore voltages reduced
Package C6 + L3 flushed and turned off, additional Uncore voltages reduced
Package C7 + most Uncore voltages reduced to 0V
Package C8 + VR12.6 in low power state
Package C9 + VR12.6 turned off
All core clocks are stopped, core state saved and voltage reduce to 0V
Cores flush L1/L2 into L3, all core clocks are stopped
Core halted, most core clocks stopped and voltage reduced to Pn
Core halted, most core clocks stopped
Core is executing code
C0
C1 C1E
C3 C6 C7 C8 C9 C10
C0
C3
C6
C7
C8
C9
C10
P
A
C
K
A
G
ST
A
TE
CORE STATE
Core behaves the same as Core C6 state
Possible combination of core/package states
Impossible combination of core/package states
Note: The “core state” relates to the core which is in the HIGHEST power state in the package (most active)
{
Advanced Configuration and Power Interface (ACPI)
States Supported
This section describes the ACPI states supported by the processor.
Table 13.
System States
State
Description
G0/S0
Full On Mode, Display On.
G0/S0
Connected Standby Mode, Display Off.
G1/S3-Cold
Suspend-to-RAM (STR). Context saved to memory (S3-Hot state is not supported by the
processor).
G1/S4
Suspend-to-Disk (STD). All power lost (except wakeup on PCH).
G2/S5
Soft off. All power lost (except wakeup on PCH). Total reboot.
G3
Mechanical off. All power removed from system.
Table 14.
Processor Core / Package State Support
State
Description
C0
Active mode, processor executing code.
C1
AutoHALT state.
C1E
AutoHALT state with lowest frequency and voltage operating point.
C3
Execution cores in C3 state flush their L1 instruction cache, L1 data cache, and L2 cache
to the L3 shared cache. Clocks are shut off to each core.
C6
Execution cores in this state save their architectural state before removing core voltage.
continued...   
4.1  
Power Management—Processors
Mobile 4th Generation Intel
®
 Core
 Processor Family, Mobile Intel
®
 Pentium
®
 Processor Family, and Mobile Intel
®
 Celeron
®
Processor Family
July 2014
Datasheet – Volume 1 of 2
Order No.: 329001-007
43