Intel 2955U CL8064701523900 Data Sheet

C7

Execution cores in this state behave similarly to the C6 state. If all execution cores

request C7 state, L3 cache ways are flushed until it is cleared. If the entire L3 cache is

flushed, voltage will be removed from the L3 cache. Power removal to SA, Cores and L3

will reduce power consumption.

C8

C7 state plus voltage is removed from all power domains after required state is saved. PLL

is powered down.

C9

C8 state plus processor V

CC

 input voltage at 0 V.

C10

C9 state plus VR12.6 is set to low-power state, near shut off.

Power up

CKE asserted. Active mode.

Pre-charge

Power-down

CKE de-asserted (not self-refresh) with all banks closed.

Active Power-

down

CKE de-asserted (not self-refresh) with minimum one bank active.

Self-Refresh

CKE de-asserted using device self-refresh.

G0

S0

C0

Full On

On

Full On

G0

S0

C1/C1E

Auto-Halt

On

Auto-Halt

G0

S0

C3

Deep Sleep

On

Deep Sleep

G0

S0

C6/C7

Deep Power-

down

On

Deep Power-down

G0

S0

C8/C9/C10

On

Deeper Power-

down

G1

S3

Power off

Off, except RTC

Suspend to RAM

G1

S4

Power off

Off, except RTC

Suspend to Disk

G2

S5

Power off

Off, except RTC

Soft Off

G3

NA

Power off

Power off

Hard off

While executing code, Enhanced Intel SpeedStep

®

 Technology optimizes the

processor’s frequency and core voltage based on workload. Each frequency and

voltage operating point is defined by ACPI as a P-state. When the processor is not

executing code, it is idle. A low-power idle state is defined by ACPI as a C-state. In

general, deeper power C-states have longer entry and exit latencies.

The following are the key features of Enhanced Intel SpeedStep Technology:

Mobile 4th Generation Intel

®

 Core

™

 Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and Mobile Intel

®

 Celeron

®

Processor Family

Datasheet – Volume 1 of 2

July 2014

44

Order No.: 329001-007