Intel i7-4600U CL8064701477000 Data Sheet

This chapter describes the processor signals. The signals are arranged in functional

groups according to the associated interface or category. The following notations are

used to describe the signal type.

I

Input pin

O

Output pin

I/O

Bi-directional Input/Output pin

The signal description also includes the type of buffer used for the particular signal

(see the following table).

CMOS

CMOS buffers. 1.05V- tolerant

DDR3L/DDR3L-

RS

DDR3L/DDR3L-RS buffers: 1.35 V-tolerant

LPDDR3

LPDDR3 buffers: 1.2 V- tolerant

A

Analog reference or output. May be used as a threshold voltage or for buffer

compensation

GTL

Gunning Transceiver Logic signaling technology

VR Enable

CMOS

Voltage Regulator Asynchronous CMOS output

Ref

Voltage reference signal

Asynchronous 

1

Signal has no timing relationship with any reference clock.

1. Qualifier for a buffer type.

SA_BS[2:0]

Bank Select: These signals define which banks are selected

within each SDRAM rank.

O

SA_WE#

Write Enable Control Signal: This signal is used with

SA_RAS# and SA_CAS# (along with SA_CS#) to define the

SDRAM Commands.

O

Mobile 4th Generation Intel

®

 Core

™

 Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and Mobile Intel

®

 Celeron

®

Processor Family

Datasheet – Volume 1 of 2

July 2014

72

Order No.: 329001-007