Intel i7-4600U CL8064701477000 Data Sheet

SB_MA[15:0]

Memory Address: These signals are used to provide the

multiplexed row and column address to the SDRAM.

O

SB_CKP[1:0]
SB_CKN[1:0]

SDRAM Differential Clock: Channel B SDRAM Differential

clock signal pair. The crossing of the positive edge of SB_CKP

and the negative edge of its complement SB_CKN are used to

sample the command and control signals on the SDRAM.

O

SB_CS#[1:0]

Chip Select: (1 per rank). These signals are used to select

particular SDRAM components during the active state. There

is one Chip Select for each SDRAM rank.

O

SB_CKE[3:0]

Clock Enable: (1 per rank). These signals are used to:
• Initialize the SDRAMs during power-up
• Power down SDRAM ranks
• Place all SDRAM ranks into and out of self-refresh during

STR

• When 1R DDR3L (SODIMM/MD) CKE[0] is used
• When 2R DDR3L (SODIMM/MD) CKE[1:0] are used

O

SB_ODT

On Die Termination: Active Termination Control.

O

SA_DQ[63:0]

Data Bus: Channel A data signal interface to the SDRAM data

bus.

I/O

SA_DQSP[7:0]
SA_DQSN[7:0]

Data Strobes: SA_DQS[7:0] and its complement signal

group make up a differential strobe pair. The data is captured

at the crossing point of SA_DQS[7:0] and its SA_DQS#[7:0]

during read and write transactions.

I/O

SA_CAA[9:0]

Command Address: These signals are used to provide the

multiplexed command and address to the SDRAM.

O

SA_CAB[9:0]

Command Address: These signals are used to provide the

multiplexed command and address to the SDRAM.

O

SA_CKP[1:0]
SA_CKN[1:0]

SDRAM Differential Clock: Channel A SDRAM Differential

clock signal pair. The crossing of the positive edge of SA_CKP

and the negative edge of its complement SA_CKN are used to

sample the command and control signals on the SDRAM.

O

SA_CS#[1:0]

Chip Select: (1 per rank). These signals are used to select

particular SDRAM components during the active state. There

is one Chip Select for each SDRAM rank.

O

SA_CKE[3:0]

Clock Enable: (1 per rank). These signals are used to:
• Initialize the SDRAMs during power-up
• Power down SDRAM ranks
• Place all SDRAM ranks into and out of self-refresh during

STR

• When 1R LPDDR3 CKE[0] and CKE[2] are used for Rank 0
• When 2R LPDDR3 CKE[0] and CKE[2] are used for Rank 0

& CKE[1] and CKE[3] are used for Rank 1

O

SA_ODT

On Die Termination: Active Termination Control.

O

Mobile 4th Generation Intel

®

 Core

™

 Processor Family, Mobile Intel

®

 Pentium

®

 Processor Family, and Mobile Intel

®

 Celeron

®

Processor Family

Datasheet – Volume 1 of 2

July 2014

74

Order No.: 329001-007