Intel C2550 FH8065401488912 Data Sheet

Product codes
FH8065401488912
Page of 746
Intel
®
 Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 2 of 3
Order Number: 330061-002US
117
Volume 2—Interrupt Architecture—C2000 Product Family
PCI Interrupts and Routing
The PIRQx register decode is shown in 
Table 6-1.
PIRQA through PIRQH Routing Register IRQ Decode
PIRQx 
Register,
IR field 3:0
PIRQx Routing
to 8259 PIC
1
1. The REN bit (bit 7) must be set to 0 or else
the PIRQx is not routed to the 8259 PIC.
The default setting of REN =1.
0000
Reserved (default)
0001
Reserved
0010
Reserved
0011
IRQ3 of the 8259 PIC
0100
IRQ4 of the 8259 PIC
0101
IRQ5 of the 8259 PIC
0110
IRQ6 of the 8259 PIC
0111
IRQ7 of the 8259 PIC
1000
Reserved
1001
IRQ9 of the 8259 PIC
1010
IRQ10 of the 8259 PIC
1011
IRQ11 of the 8259 PIC
1100
IRQ12 of the 8259 PIC
1101
Reserved
1110
IRQ14 of the 8259 PIC
1111
IRQ15 of the 8259 PIC