Intel C2550 FH8065401488912 Data Sheet
Product codes
FH8065401488912
Intel
®
Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 2 of 3
Order Number: 330061-002US
119
Volume 2—Interrupt Architecture—C2000 Product Family
System Control Interrupt (SCI)
6.4
System Control Interrupt (SCI)
SCI is a special type of hardware power-management interrupt that is handled directly
by the OS, and is not handled by a device driver. It is closely tied to the ACPI model.
The operating system uses the SCI interrupt to process ACPI events signaled by GPEs,
whether the system is asleep or awake when the event occurs.
SCI can be useful in cases where a driver is not loaded. For example, when a device
has been placed in the D3 power state while the system remains in S0, or for the
delivery of events such as power button to the OS.
If not using the I/O APIC for the SCI, the SCI must be routed to IRQ9-IRQ11 of the
8259 PIC. When routed to the 8259 PIC, the SCI is not sharable with the Serial
Interrupt (SERIRQ) for that PIC input, but it is shareable with the PIRQA through
PIRQH interrupts.
If using an I/O APIC, the SCI is mapped to the I/O APIC interrupt or to an SMI.
Mapping SCI events to SMI can be used when a legacy (APM) OS is in use. The SCI
Enable (SCI_EN) bit of the Power Management 1 Control (PM1_CNT) register controls
whether the event is routed as an SCI or an SMI. The PM1_CNT register is located in
the I/O space at ACPI_BASE_ADDRESS, offset 4.
The SCI routing to the I/O APIC is controlled by the 3-bit SCI IRQ Select (SCIS) field of
the ACPI Control (ACTL) register located in the memory space at
Also, if using the I/O APIC for SCI, the SCI can be mapped to IRQ20-IRQ23 of the I/O
APIC, and can be shared with other interrupts. Here the SCI must be programmed for
active-low reception. The SCI can also be mapped to IRQ9, IRQ10, of IRQ11 where it
must be programmed for active-high reception.
6.5
Message Signaled Interrupt (MSI and MSI-X)
MSI and MSI-X are generated by PCI and PCI Express devices that have this capability.
During device configuration, each capable PCI function is allocated one or more vectors
and the memory-mapped location to write the interrupt messages. When written in to
memory, the MSI is communicated to the appropriate CPU through its local APIC.
Table 6-2.
Routing of SCI to the I/O APIC
ACTL.SCIS
I/O APIC Input to
Which the SCI is
Routed
000
IRQ9
001
IRQ10
010
IRQ11
011
SCI Disabled
100
IRQ20
101
IRQ21
110
IRQ22
111
IRQ23