Intel C2550 FH8065401488912 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

138

Order Number: 330061-002US

1.

Some pin-based hard straps are sampled before COREPWROK is asserted. The SoC latches these strap 

values when COREPWROK transitions to the asserted state.

2.

Reference Clock input-pin signals are:

HPLL_REF[P, N] (differential input)

PCIE_REFCLK[P, N] (differential input)

SATA_REFCLK[P, N] (differential input)

SATA3_REFCLK[P, N] (differential input)

GBE_REFCLK[P, N] (differential input)

USB_REFCLK[P, N] (differential input)

3.

When the SoC output signal PMU_PLTRST_B is used by the platform board design to provide PCI 

Express* components or add-in adapter cards the PCI Express* Fundamental Reset signal called 

PERST#, refer to Section 2.6.2 of the PCI Express Card Electromechanical Specification, Revision 2.0. It 

specifies special Power Sequencing and Reset Signal Timings that supersede the t33 parameter in this 

table.

4.

The Min parameter allows satisfying the 30-µs minimum requirement show in Figure 9: Timing for 

Entering and Exiting the Power Down of the Intel Low Pin Count (LPC) Interface Specification, Revision 

.

This SoC output signal allows the platform board, as an option, to power-down the SoC 

SUS well during the S5 state. The SoC does not support this situation and so the 

SUSPWRDNACK output signal is always inactive during a Cold Reset sequence. 

The SoC does assert the SUSPWRDNACK signal for a brief period after the SUS well 

voltages are powered-on. See 

.

t33

COREPWROK asserted after all DDR3 and Core 

voltages are valid and all Reference Clocks stable at 

SoC input pins

10

-

 ms

1, 2, 3

t34

COREPWROK, DDR3_0_VCCA_PWROK, and 

DDR3_1_VCCA_PWROK active logic-level duration 

required to be sensed as valid by the SoC.

1

-

ms

t35

PMU_PLTRST_B de-asserted after SUS_STAT_B de-

asserted

60

100

 µs

4