Intel C2550 FH8065401488912 Data Sheet

Product codes
FH8065401488912
Page of 746
Intel
®
 Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 2 of 3
Order Number: 330061-002US
139
Volume 2—SoC Reset and Power Supply Sequences—C2000 Product Family
Reset Sequences and Power-Down Sequences
7.2.2
Warm Reset Sequence
From a platform board perspective, the SoC initiates a Warm Reset sequence while in 
the S0 (Working) state. The situations when this occurs are shown as Reset Type 1 in 
.
A Warm Reset sequence is the same as the Cold Reset except that the SoC SUS well, 
DDR3 power, and Core well power remain on during the entire sequence. The platform 
also provides valid reference clocks to the SoC during the entire Warm Reset sequence. 
Refer to 
:
1. The SoC issues a Platform Reset (PMU_PLTRST_B).
2. The SoC remains in the S0 (Working) state.
3. The SoC ends the Platform Reset.
4. The SoC re-boots the BIOS and operating system.
Figure 7-6. Warm Reset Sequence
t
56
SoC output: 
PMU_PLTRST_B
SoC output: 
SUS_STAT_B
SoC output: 
CPU_RESET_B
t
35
SoC inputs asserted during entire period:
DDR3_0_DRAM_PWROK
DDR3_1_DRAM_PWROK
COREPWROK
DDR3_0_VCCA_PWROK
DDR3_1_VCCA_PWROK
SoC outputs de-asserted during entire period:
SUSPWRDNACK
PMU_SLP_S45_B
PMU_SLP_S3_B
PMU_SLP_DDRVTT_B
RTC power well, SUS power well, and Core power 
well voltages are valid during this entire period
SoC inputs de-asserted during entire period: 
RTEST_B
SRTCRST_B
RSMRST_B