Intel C2550 FH8065401488912 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

200

Order Number: 330061-002US

The SGMII link mode is used when external PHY components are used. For proper 

network operation, both the LAN Port MAC and the external PHY component must be 

properly configured, either explicitly via software or via hardware auto-negotiation, 

with identical speed and duplex settings. The SGMII Auto-Negotiation functionality is 

similar to what is defined in Clause 37 of the IEEE Standard 802.3-2008. The GbE 

controller provides an external MDIO/MDC interface to configure external PHYs 

connected to the LAN Port SGMII interface. See 

Refer to Appendix D of the Intel

Design Guide (PDG) for guidance on which external PHYs are supported.

Each GbE controller LAN Port can provide MAC loopback where the controller’s internal 

serial/deserial unit is not functional and data sent by the SoC root complex is fed-back 

to the root complex. Each LAN port also has the loopback capability where the serial/

deserial unit is functional and the data normally sent over the LAN Port interface to the 

backplane or external PHY is instead fed-back to the serial/deserial unit and back to the 

root complex.

For detailed information on configuring, auto negotiation, Ethernet flow control, 

loopback and controlling the LAN Ports and external PHYs, see the Intel

Manual (PRM). Also refer to the PRM for these LAN Port features:

• Device power management and power states
• DMA Coalescing
• Broadcast Wake Up
• IPv4/IPv6 packet-detect support
• Magic Packet detection and operation
• Packet pattern flexible filters

. Board design guidelines are given in the Intel

Processor C2000 Product Family Platform Design Guide (PDG).