Intel C2550 FH8065401488912 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

203

The GbE controller provides two Software-Defined Pins (SDP) for IEEE 1588 auxiliary 

device connections and other miscellaneous hardware- or software-control purposes. 

These pins, and their functions, are bound to a specific LAN device. The pins can be 

individually configured to act as standard inputs, General-Purpose Interrupt (GPI) 

inputs, or output pins.

The use, direction, and values of SDP pins are controlled and accessed in each PCI 

function’s Memory-Mapped I/O (MMIO) using fields in the Device Control (CTRL) 

register (MMIO offset 0, and aliased at offset 4h) and the 32-bit Extended Device 

Control (CTRL_EXT) register (MMIO offset 18h).

The internal SDP ports are routed to the SoC pins based on the programmable GbE 

SDPs Mux Control (SDPS_MUX_CTRL) register located at MMIO offset 8134h for each 

PCI function.

The default direction of each of the pins is configurable via the EEPROM as well as the 

default value of any pins configured as outputs. To avoid signal contention, all pins are 

set as input pins until after the EEPROM configuration has been loaded by the GbE 

controller. Each of the four LAN Ports has a 

 register 

located at 16-bit word offset 20h from the LAN Ports base address in EEPROM. The four 

base address values, 0h, 80h, C0h, and 100h, are shown in 

.

In addition to all pins being individually configurable as inputs or outputs, they can be 

configured for use as General-Purpose Interrupt (GPI) inputs. To act as GPI pins, the 

desired pins must be configured as inputs. A separate GPI interrupt-detection enable is 

then used to enable rising-edge detection of the input pin (rising-edge detection occurs 

by comparing values sampled at the internal clock rate as opposed to an edge-

detection circuit). When detected, a corresponding GPI interrupt is indicated in the 

Interrupt Cause Read (ICR) register located at MMIO offset 1500h for each PCI 

function.

For addition information concerning the CTRL register, CTRL_EXT register, the EEPROM 

registers, and SDP control and operation, refer to the Intel

Product Family Integrated GbE Controller Programmer’s Reference Manual (PRM).

Electrical and timing specifications are in 

. Board design guidelines are given in the Intel

Atom™ Processor C2000 Product Family Platform Design Guide (PDG).