Intel C2550 FH8065401488912 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

270

Order Number: 330061-002US

See Chapter 8 of the Universal Serial Bus Specification, Revision 2.0.

See Chapter 8 of the Universal Serial Bus Specification, Revision 2.0.

The initialization sequence expected by the EHC is described here.

The sequence begins with a complete power cycle in which the Suspend (SUS) power 

well and Core power well have been off.

The Suspend (SUS) power well is a lower-power plane than the core power well. The 

SUS well is always functional when the core well is functional, but the core well is not 

functional when the SUS well is functional. Therefore, the SUS well reset pin 

) deasserts before the core well reset pin (

) rises. The SUS 

well reset deasserts leaving all registers and logic in the SUS well in the default state. 

However, reading any registers does not occur until after the core well reset deasserts. 

Normally the SUS well reset only occurs when a system is unplugged (or the battery is 

removed). In other words, SUS well resets are not easily achieved by the software or 

the end user. This step typically does not occur immediately before the remaining 

steps.

The core well reset deasserts, leaving all registers and logic in the core well in the 

default state. The EHC configuration space is accessible at this point. 

The core well reset occurs (and typically does) without the SUS well reset asserting. 

This means that all of the Configure Flag and Port Status and Control bits (and any 

other SUS-well logic) are in any valid state at this time.

) are at their default values. After a 

hardware-based reset, only the Operational Registers not contained in the SUS power 

well are at their default values.

The policy to disable the EHC functionality cannot be dynamic. If the EHC must be 

disabled in the system, the BIOS must set the corresponding function disable bit before 

any accesses are made to the EHC (configuration or memory space). Once set, this 

disable bit must remain set until a hardware reset occurs.

When the system boots the host controller is enumerated and assigned a base address 

for the register space, the BIOS sets the Frame Length Adjustment register located in 

the configuration space at bus 0, device 22 (decimal), function 0, offset 60h.

The BIOS performs a number of platform-customized steps after the Core power well 

has powered-up. Contact the Intel Field Representative for additional BIOS information 

for the SoC.