Intel C2550 FH8065401488912 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

272

Order Number: 330061-002US

This section provides a brief overview of the USB core operation and data flow. The 

USB2 Enhanced Host Controller (EHC) conforms to the Enhanced Host Controller 

Interface Specification for Universal Serial Bus, Revision 1.0 and supports the 

programming model described in the specification. See 

.

To initialize the host controller, the software (USB driver) performs the steps required in 

the EHCI Specification and configure all the relevant registers, which include:

At this point, the host controller is up and running and the port registers begin 

reporting device connects, etc. The system software enumerates a port through the 

reset process (where the port is in the enabled state). At this point, the port is active 

with Start of Frame (SOF) packets occurring at the enabled ports.

To enable USB transactions on the bus, the driver configures the Periodic Frame List 

and Asynchronous Transfer List data structures in the memory.

The data structures are used to communicate control, status, and data between the 

software and the host controller. The Periodic Frame List is an array of pointers for the 

periodic schedule. A sliding window on the Periodic Frame List is used. The 

Asynchronous Transfer List is where all the control and bulk transfers are managed and 

is a simple circular list of queue heads. Refer to the EHCI Specification for more details 

regarding the data structure format.

In each micro-frame, the host controller engine executes from the Periodic Schedule 

before executing from the Asynchronous Schedule. This engine only executes from the 

asynchronous schedule after it encounters the end of the periodic schedule (the 

software driver makes sure that the periodic schedule does not starve the 

asynchronous one).

The DMA engine fetches the element from the appropriate schedule and begins 

traversing the graph of linked schedule data structures, by issuing appropriate non-

posted read requests to system memory. The DMA engine then analyzes the 

completion indications from the SoC memory controller.

The DMA engine starts executing the transaction on the bus once enough space is in 

the appropriate payload buffer (maximum-size frame for IN transactions) or a complete 

transaction is residing in the buffer for OUT transactions. Each DMA engine always 

operates on two transactions, one that is currently being executed on the bus and one 

that is actively being fetched from or stored to the memory. To achieve this 

functionality each DMA engine contains a double-buffer per direction. Each buffer is 

able to accommodate two maximum transactions. For Periodic DMA buffer size 1.5 KB 

and the Asynchronous DMA buffer size is 1 KB.