Intel C2550 FH8065401488912 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

312

Order Number: 330061-002US

For writes going out from SMT to the SMBus, the PEC is calculated by the hardware and 

appended. For reads, the PEC byte is received from the target and verified by the 

hardware (incorrectness notification is provided to the firmware by the status bits). The 

PEC byte is not sent to the buffer.

Firmware-specific:

1. If the firmware wants to send a large amount of data (more than 32-data bytes 

without counting command byte and byte count) to a target using SMBus 2.0 

protocol and indicates to the hardware to send data using block write protocol, it is 

the responsibility of the firmware to break the data into multiple packets and set up 

individual descriptors for each packet.

2. The firmware honors all SMBus 2.0 rules for transactions of write, read, transcribe 

of the total data transfer on SMBus being not more than 32 bytes (including 

BlockWr-BlockRd process call).

3. The firmware sets the PEC bit when initiating a PEC-accompanied read from a 

target so that the hardware verifies and reports PEC accuracy, or when initiating a 

PEC-accompanied write transaction so that the hardware automatically appends the 

PEC byte.

4. The firmware must clear the I

2

C bit when initiating SMBus transactions.

5. Because a single pointer is used, for SMBus transactions which both transmit and 

receive data (i.e., Process Call and Block Write-Block Read Process Call), the 

received data overwrites the transmitted data. Before beginning the transaction, 

firmware must copy the transmit data if the transmit data are preserved after the 

transaction.

For I

2

C transactions, 

 illustrates how the hardware uses the control 

information in the descriptor. The following are the I

2

C support limitations:

1. Support is limited to 7-bit addressing mode only.
2. Write-Read Combined format is supported with SMT as master.
3. As a target, the hardware supports only writes initiated by an external master.

I

2

C Writes

(MTx-to-SRx)

1

Command 

(1 byte of 

write data)

0

0

X

X

I

2

C Writes

(MTx-to-SRx)

0

2 or more

0

0

Points to transmit 

buffer containing at 

least 2 bytes of write 

data.

X

I

2

C Reads

(STx-to-MRx)

0

0

1 or more

1

X

Points to the 

receive buffer 

where the receive 

data are placed.

1.

This table assumes the target address is programmed in the descriptor and is not part of the WRLNTH 

field.

2.

The I

2

C bit must be set for all I

2

C transactions.

3.

PEC is not supported for any I

2

C transaction.

4.

The BLK bit must be 0 for all I

2

C transactions.