Intel C2550 FH8065401488912 Data Sheet

Product codes
FH8065401488912
Page of 746
Intel
®
 Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 2 of 3
Order Number: 330061-002US
313
Volume 2—SMBus 2.0 Unit 1 - Host—C2000 Product Family
Controller Characteristics and Operation
I
2
C Combined 
Format (write 
followed by 
read)
1
Command 
(1 byte of 
write data)
1 or more
0
X
Points to the 
receive buffer 
where the receive 
data are placed.
I
2
C Combined 
Format (write 
followed by 
read)
0
2 or more
1 or more
0
Points to transmit 
buffer containing at 
least 2 bytes of write 
data
Points to the 
receive buffer 
where the receive 
data are placed.
Table 15-15. I
2
C Commands (Continued)
I
2
C
Command
C/WRL
WRLNTH
RDLNTH
RW
(0=W;
1=R)
DPTR
(points to TX data)
DPTR
(points to RX 
data)
Notes:
1.
This table assumes the target address is programmed in the descriptor and is not part of the WRLNTH 
field.
2.
The I
2
C bit must be set for all I
2
C transactions.
3.
PEC is not supported for any I
2
C transaction.
4.
The BLK bit must be 0 for all I
2
C transactions.