Intel C2550 FH8065401488912 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

329

External Master Initiating Reads:

1. Once the hardware receives a read transaction targeting one of its slave addresses, 

the hardware checks the address, command, and any other bytes sent by the 

external master and ACK/NACK appropriately.

2. If all the bytes sent by the external initiator are ACKed by the hardware, the 

hardware provides read data to initiator. (See 

.)

a. If initiator takes all bytes as expected and terminates transaction normally, 

depending on the state of TCTRL.SCHWBP bit, the hardware creates (or does not 

create) a header Dword and write to memory at location pointed by HWtHeadPtr, 

with BC field updated.

b. If error conditions are read, the hardware updates the error status registers in 

the status Dword, create the header with the appropriate BC field, and write to 

memory at location pointed by HWtHeadPtr.

3. The hardware then updates the HWtHeadPtr to the next free Dword location in the 

target memory.

4. The hardware then writes interrupt information to the Dwords as pointed to by 

SMTICL. (See 

.)

a. The hardware writes the current value of HWtHeadPtr to TRGT.HTHP and sets 

TRGT.VALID.

b. Also, if the transaction terminated abnormally the error condition is written 

(e.g., to ERR.TRBAF, ERR.TRBF, ERR.CKLTO) and ERR.VALID is set to indicate an 

error was present.

c. Finally, if enabled, the hardware then sends MSI to the firmware.