Intel C2550 FH8065401488912 Data Sheet

Product codes

FH8065401488912

Volume 2—SMBus 2.0 Unit 1 - Host—C2000 Product Family

Controller Characteristics and Operation

Intel

Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

330

Order Number: 330061-002US

15.4.8.5

Target Flow

Target flow for the hardware depends on the target address seen on the SMBus. The

hardware has deterministic behavior based on the address. A high-level flowchart is

shown in

Figure 15-9

. It does not capture all possibilities of errors, but aims to

highlight the sequence of events. Depending on the received address, detailed

flowcharts follow in later sections for four protocol categories.

The hardware address matching after an SMBus start condition is subject to

SUSCHKB.IRWST; if asserted it causes the hardware to ignore the R/W# bit during

matching. This behavior is not shown in the flowchart. It does have implications for

how Quick Command, Receive Byte, and I

C Read are handled.

Figure 15-9. High-Level Target Flow

Address == 10h?

IDLE

Address+R/W

Received

SMBus Start

Address == C2h?

Address ==

GPBRCTRL.GPTRADR?

Address ==

TACTRL.ADDR0 ||

TACTRL.ADDR1?

Yes

Host address enabled?

TPOLICY.Host_SMBADDR_EN

Cleared

Set

Default address enabled?

TPOLICY.DEF_SMBADDR_EN

Cleared

Set

GPBR address

enabled?

GPBRCTRL.EN

Cleared

Set

Slave address enabled?

TPOLICY.ADDR0_EN
TPOLICY.ADDR1_EN

Cleared

Set

Target mode enabled?

TPOLICY.TGTEN

Set

Cleared

Yes

ACK

Jump to

“Host Notify”

Flow

Jump to

“ARP”

Flow

Jump to

“GPBR”

Flow

Jump to

“SMBus/I

C”

Flow

NACK

ACK