Intel C2550 FH8065401488912 Data Sheet
Product codes
FH8065401488912
Intel
®
Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 2 of 3
Order Number: 330061-002US
503
Volume 2—Low Pin Count (LPC) Controller—C2000 Product Family
Architectural Overview
24.2.2
LPC Flash Programming Considerations
24.2.2.1
Overview
The Low Pin Count (LPC) interface can be used for connection of various legacy
components including: an EC, Super I/O, TPM, FWH. The SoC does NOT support
bus-mastering devices on LPC such as Bi-Dir Parallel Port, IR, or Floppy Drive.
This section details BIOS programming considerations for the Firmware Hubs (FWH)
located on the LPC.
Note:
Only the non-descriptor mode can be used when booting to the BIOS from FWH on the
SoC.
The following features are not supported when using LPC (FWH):
• Soft Straps
• Multiple SPI Flash components
• Non-Contiguous Regions
• Direct write of the Flash
• Hardware sequencing cannot be used, software sequencing must be used
• Multiple SPI Flash components
• Non-Contiguous Regions
• Direct write of the Flash
• Hardware sequencing cannot be used, software sequencing must be used
For compatibility with the LPC FWH interface, the SPI interface supports decoding the
two 64 KB BIOS ranges at the E0000h and F0000h segments just below 1 MB. These
ranges must be re-directed (aliased) to the ranges just below 4 GB by the controller.
This is done by forcing the upper address bits [23:20] to 1s when performing the read
on the SPI interface.
Note:
In non-descriptor mode, the SoC will run the BIOS direct read cycle at 20 MHz.