Intel C2550 FH8065401488912 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

505

The LPC interface supports accessing the Intel

®

 Trusted Platform Module (Intel

®

 TPM) 

1.2 devices via the LPC TPM START encoding. Software should continue to use the 

memory mapped 0xFED4_xxxx address range to access the SPI-TPM or the LPC-TPM. 

No additional checking of the memory cycle is performed.

Since Intel

®

 Trusted Execution Technology (Intel

®

 TXT) transactions are not supported 

by the SoC, this memory-address range is different than the FED0_0000h to 

FED4_BFFFh range implemented on some other Intel components.

The LPC Controller is a 32-bit addressed device that sits under the Platform Controller 

Unit (PCU). These two units make up the System Subtractive Agent for the SoC. This 

means that a posted or non-posted request targeted for the Memory Mapped I/O 

(MMIO) or I/O space that is not positively decoded in the SoC will be sent to the 

PCU/LPC Controller. Here are the rules the SoC follows for all requests that are not 

positively decoded.

PCU

If an I/O address:

— Forward request to the LPC Controller

If MMIO address < 4 GB:

— Forward request to the LPC Controller 

If MMIO address => 4 GB:

— For a read, return an Unsupported Request (UR).
— For a write, it will be silently dropped.

LPC Controller

If an I/O address:

— Place request on the LPC bus (asserts LPC_FRAME_N), if not claimed.
— For a read, return an Unsupported Request (UR).
— For a write, it will be silently dropped.

If MMIO address:

— Place request on the LPC bus, if not claimed.
— For a read, return an Unsupported Request (UR).
— For a write, it will be silently dropped.

To maintain backwards compatibility with older MMIO LPC devices that can only handle 

addresses < 16 MB, the LPC Controller allows masking the LPC_FRAME_N, if the MMIO 

address is > 16 MB. See register in 

.