Intel C2550 FH8065401488912 Data Sheet

Product codes
FH8065401488912
Page of 746
Volume 2—System Agent and Root Complex—C2000 Product Family
Global Error Reporting
Intel
®
 Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
72
Order Number: 330061-002US
4.7.1
Reporting Errors to CPU
Detected errors are forwarded to the CPU using either an NMI or SMI.
4.7.1.1
Non-Maskable Interrupt (NMI)
Any error can be mapped to an NMI. However, NMIs are typically used to report fatal 
errors. When an error triggers, an NMI is generated to the CPU.
4.7.1.2
System Management Interrupt (SMI)
Any error can be mapped to an SMI. SMIs are typically used to report fatal, non-fatal, 
or correctable error conditions in the SoC. When an error triggers, an SMI is generated 
to the CPU.
4.7.2
Reporting Global Errors to an External Device
Detected errors are forwarded to an external device, a BMC for example, using the 
following active low, three error pins (see 
4.7.3
Machine Check Architecture
This section provides the necessary details for the operating software to handle 
Machine Check Exceptions (MCE). Some operating systems hook the Machine Check 
Architecture (MCA) exception vector (18h) to allow system-crash analysis. Like some 
other Intel processors, the SoC has been enhanced to allow the machine state to be 
preserved across the assertion of the RESET# signal. The BIOS does not modify the 
MCA registers following the RESET# assertion. This allows the operating system to 
enhance the exception handler by having this information available following a reboot 
after an error has occurred. Only upon the assertion (the signal transition from low to 
high) of the COREPWROK input signal (indicating POWERGOOD, power-on) is the 
machine-check architecture state re-initialized.
All MCA state information is accessible via the Model-Specific Register (MSR) accesses 
using the Read MSR (RDMSR) and Write MSR (WRMSR) instructions. RDMSR and 
WRMSR are described in Volume 2, Chapter 4 of the Intel
®
 64 and IA-32 Architectures 
Software Developer’s Manual. See 
.
There are three major classifications of MCA MSRs:
1. Global Control registers
2. Error-Reporting Bank registers
3. Extended Machine-Check State registers
The SoC does not have any MCA Extended Machine Check State registers. The first two 
classifications are shown in