Intel C2550 FH8065401488912 Data Sheet
Product codes
FH8065401488912
Volume 2—System Agent and Root Complex—C2000 Product Family
Global Error Reporting
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
88
Order Number: 330061-002US
4.7.4
Error-Status Cloaking Feature
Error-status cloaking is an error management feature that allows the platform board
management firmware to intercept corrected and uncorrected errors before the
operating system software reads and clears the error log.
A new Model-Specific Register (MSR) has been added to enable or disable this feature.
SMM_MCA_CONTROL is a 64-bit register at MSR 52h which contains 2 bits for this
feature. This MSR is accessible only while the thread is executing in the System
Management Mode (SMM). There is an SMM_MCA_CONTROL MSR register for each
logical processor (has a thread scope). If accessed when not in SMM, a
.
4.7.4.1
Hide Corrected-Error Status From OS
Normally, corrected errors are reported through the IA32_MCi_STATUS registers which
are accessible through the Read MSR (RDMSR) and Write MSR (WRMSR) instructions.
Even though the SoC does not support Corrected Machine Check Interrupt (CMCI),
these errors are logged in IA32_MCi_STATUS and are visible to the operating system.
Here the IA32_MCi_STATUS contains the Valid bit = 1 (bit 63), the Uncorrected Error
bit = 0 (bit 61), and the Processor Context Corrupted (PCC) bit = 0 (bit 57).
When the cloaking feature is enabled (SMM_MCA_CONTROL[0] =1), the operating
system is prevented from reading these logged valid corrected errors unless the
software is operating in the SMM. If not in SMM with the cloaking feature enabled, the
RDMSR instruction can access IA32_MCi_STATUS, but the instruction returns 0 even
though the valid corrected error(s) is logged.
This feature can be dynamically enabled/disabled.
4.7.4.2
SMI for MCA Uncorrected Errors
When the PEND_SMI_ON_MCA feature is enabled (SMM_MCA_CONTROL[9] =1), a
System Management Interrupt (SMI) is made pending whenever the Machine Check
Architecture (MCA) mechanism processes uncorrectable errors. Here the
IA32_MCi_STATUS contains the Valid bit = 1 (bit 63), the Uncorrected Error bit = 1 (bit
61), and the Processor Context Corrupted (PCC) bit = 0 (bit 57).
This feature can be dynamically enabled/disabled.
Table 4-10. SMM_MCA_CONTROL - MSR 52h - Enable/Disable Error-Status Cloaking
Feature
Bits
Default
Name
RDMSR
WRMSR
Action
63:10
0
Reserved
0
#GP
1
1. A General-Protection Exception (#GP) is generated.
9
0
PEND_SMI_ON_MCA
Allowed
Allowed
Post a pending SMI
8:1
0
Reserved
0
#GP
1
0
0
CERR_RD_STATUS_IN_SMM_ONLY
Allowed
Allowed
When 1, a valid corrected
error status (V = 1, UC = 0,
PCC = 0) is visible only
when read in SMM. If not in
SMM, a 0 status is returned
for the valid corrected
errors.