Intel C2550 FH8065401488912 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

90

Order Number: 330061-002US

The SoC contains a set of error registers to support error reporting. These error 

registers are assumed to be sticky unless specified otherwise. Sticky means the 

register values are retained even after a hard reset

—

they are only cleared by the 

software or by a power-on reset.

The two levels of hierarchy for the error registers are:

• Local Error registers
• Global Error registers

The Local Error registers are associated with the SoC local devices (GbE, SMBus, Root 

Complex, PCIe Root Ports, SoC system agent, memory controller, SATA2, SATA3, USB2 

and platform controller unit). The Global Error registers collect the errors reported by 

the Local Error registers and map them to system events.

The four types of local devices are:

• Non-PCI devices
• Legacy PCI devices
• PCI Express devices
• PCI Express Root Ports

The non-PCI devices, the SoC memory controller as an example, directly report errors 

to the global error logic. These devices use a proprietary mechanism for reporting 

errors to the global error logic.

The legacy PCI devices (SATA2, SATA3, USB2 and the platform controller unit) have 

limited error-logging capabilities. These devices support PCI registers and report errors 

to the global error logic.

The PCIe root complex integrated endpoints (GbE, SMBus, and Root Complex) 

implement the PCIe Advanced Error Reporting (AER) capability and report errors to the 

global error logic through the Root Complex Event Collector (RCEC). These PCIe 

integrated endpoint devices support AER registers for logging and reporting 

internal-fabric and device-specific errors. Device-specific errors are logged in the Local 

Error registers and reported.

These PCIe integrated endpoint devices generate the PCIe error messages ERR_CORR, 

ERR_NONFATAL, and ERR_FATAL to the RCEC. These are errors that originate from the 

Root Complex. 

The RCEC also supports the PCIe AER capability and generates INTx/MSI interrupts per 

the PCI Express Base Specification, Revision 2.1. The errors reported to the RCEC 

optionally signal to the SoC global error logic according to their severities through the 

programming of the PCIe Root Control register (ROOTCTL). Messages are generated, 

logged, forwarded, and ultimately notified to the global error logic.

The PCIe Root Ports support the PCIe AER capability and generate INTx/MSI interrupts 

per the PCI Express Base Specification, Revision 2.1. Also, the PCIe Root Ports 

optionally signal to the SoC global error logic according to their severities through the 

programming of the PCIe Root Control register (ROOTCTL). When the system error 

reporting is enabled for the specific PCIe error type, the SoC maps the PCIe error to the 

SoC error severity and reports the error to the Global Error Status register.