Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

129

Refer to 

. At this point the SoC either:

• If 

 the After G3 Enable (AG3E) hard pin strap (SoC 

pin Y65, see 

) determines the next 

sequence of events. This hard pin strap was sensed when the standby power-up 

sequence completed (

):

— SoC pin Y65 = logic low: The SoC exits S5 and proceeds with sequence to 

ultimately get to the S0 state.

— SoC pin Y65 = logic high: The SoC remains in S5 until a Wake Event occurs 

(e.g., PMU_PWRBTN_B active for less than 4 seconds). When the event occurs, 

it proceeds with sequencing to ultimately get to the S0 state.

If the platform board does not have an RTC coin battery or if the RTC battery voltage is 

not valid, the SoC is always in a 

 situation as it 

transitions from the G3 to S5 state.

• If  not 

— AG3E register = 0: The SoC exits S5 and proceeds with sequence to ultimately 

get to the S0 state.

— AG3E register = 1: The SoC remains in S5 until a Wake Event occurs (e.g., 

PMU_PWRBTN_B active for less than 4 seconds). When the event occurs, 

proceed with sequencing to ultimately get to the S0 state.

BIOS can write the AG3E register bit for use on subsequent G3-to-S5 transitions. Only 

the 

 situation uses the AG3E hard pin strap for this 

purpose.

The Wake Events are listed in 

.

When the SoC proceeds, it does so by exiting the S5 state and deasserting the active-

low SoC output signal PMU_SLP_S45_B. At this time, the SoC is ready to begin 

receiving the DDR3 and core-well voltages and remaining reference clocks from the 

platform board.

The platform board may now begin to apply power to the DDR3 circuitry and to the 

core power well of the SoC. These voltage groups are considered “switched” voltages in 

that they are not always on like the standby voltage groups. Some of the voltage group 

names have the suffix “S.”

During this power-up sequence, the platform board continues to deassert the active-

high SoC COREPWROK input signal indicating that the Core power-well pins do not have 

their valid voltage levels, and the reference clocks are not valid and stable.

All voltage-supply sequencing requirements given in this chapter are specified at the 

SoC pins/balls.