Intel C2518 FH8065501516710 Data Sheet
Product codes
FH8065501516710
Intel
®
Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 2 of 3
Order Number: 330061-002US
131
Volume 2—SoC Reset and Power Supply Sequences—C2000 Product Family
Power Up from G3 State (Mechanical Off)
Notes:
1.
Some pin-based hard straps are sampled before COREPWROK is asserted. The SoC latches these strap
values when COREPWROK transitions to the asserted state.
2.
Reference Clock input-pin signals are:
HPLL_REF[P, N] (differential input)
PCIE_REFCLK[P, N] (differential input)
SATA_REFCLK[P, N] (differential input)
SATA3_REFCLK[P, N] (differential input)
GBE_REFCLK[P, N] (differential input)
USB_REFCLK[P, N] (differential input)
3.
When the SoC output signal PMU_PLTRST_B is used by the platform board design to provide PCI
Express* components or add-in adapter cards the PCI Express* Fundamental Reset signal called
PERST#, refer to Section 2.6.2 of the PCI Express Card Electromechanical Specification, Revision 2.0. It
specifies special Power Sequencing and Reset Signal Timings that supersede the t33 parameter in this
table.
4.
The Min parameter allows satisfying the 30-µs minimum requirement show in Figure 9: Timing for
Entering and Exiting the Power Down of the Intel Low Pin Count (LPC) Interface Specification, Revision
1.1
.
The platform board may now begin to apply power to the DDR3 circuitry and to the
Core power well of the SoC. These voltage groups are considered “Switched” voltages
in that they are not always on like the standby voltage groups. Some of the voltage
group names have the suffix “S.”
During this power-up sequence, the platform board continues to drive the active-high
SoC input COREPWROK low indicating that the Core power well pins do not have their
valid voltage levels and the reference clocks are not valid and stable.
Note:
All voltage-supply sequencing requirements are given as measured at the SoC pins/
balls.
Table 7-2.
S5 State to the S0 State Sequence - Not Cold Reset
Sym
Parameter
Min
Max
Units
Note
Fig
t33
COREPWROK asserted after all DDR3 and Core
voltages are valid and all Reference Clocks stable
at SoC input pins
10
-
ms
1, 2, 3
t34
COREPWROK, DDR3_0_VCCA_PWROK, and
DDR3_1_VCCA_PWROK active logic-level duration
required to be sensed as valid by the SoC.
1
-
ms
-
“COREPWROK” hard strap value hold time after
COREPWROK asserted by platform board
400
-
ns
1
t35
PMU_PLTRST_B de-asserted after SUS_STAT_B de-
asserted
60
100
µs
4
tAVN001
SUSPWRDNACK de-asserts after
PMU_SLP_DDRVTT_B de-asserts
-
200
ns