Intel C2518 FH8065501516710 Data Sheet
Product codes
FH8065501516710
Intel
®
Atom™ Processor C2000 Product Family for Microserver
September 2014
Datasheet, Vol. 2 of 3
Order Number: 330061-002US
133
Volume 2—SoC Reset and Power Supply Sequences—C2000 Product Family
Reset Sequences and Power-Down Sequences
7.2
Reset Sequences and Power-Down Sequences
The SoC remains in the S0 (Working, or Fully-On) until some event causes it to:
1. Perform a Cold Reset, or
2. Perform a Warm Reset, or
3. In an orderly fashion, transition to, and remain in the S5 (Soft Off) state, or
4. In a quick fashion, transition to, and remain in the S5 (Soft Off) state, or
5. In an orderly fashion, transition to and remain in the G3 (Mechanical Off) state.
2. Perform a Warm Reset, or
3. In an orderly fashion, transition to, and remain in the S5 (Soft Off) state, or
4. In a quick fashion, transition to, and remain in the S5 (Soft Off) state, or
5. In an orderly fashion, transition to and remain in the G3 (Mechanical Off) state.
In some cases, before the SoC exits from the S0 state, the event causing the exit is
retained by the SoC and preserved by the SUS well voltage or by the RTC battery
voltage. The retained information is used by the SoC to transition back to S0 in the
appropriate manner.
7.2.1
Cold Reset Sequence
From a platform board perspective, the SoC initiates a Cold Reset sequence while in the
S0 (Working) state. The situations when this occurs are shown as Reset Types 2 and 4
.
During the entire Cold Reset sequence, the platform maintains valid voltage levels for
the SoC SUS well (Standby power). The following 20-step sequence is performed.
for sequence steps 1 through 9:
1. The SoC begins the sequence by asserting the active-low SUS_STAT_B output
signal to the platform board.
2. The SoC initiates a Platform Reset by asserting the active-low PMU_PLTRST_B
output signal to the platform board.
3. The SoC asserts the active-low PMU_SLP_S3_B and PMU_SLP_DDRVTT_B output
signals to the platform board.
— This indicates that the SoC has entered the S3 state. This occurs even though
the SoC does not support the Suspend to RAM sleep state (S3).
4. The platform board responds by deasserting the active-high COREPWROK,
DDR3_0_VCCA_PWROK, and DDR3_1_VCCA_PWROK input signals of the SoC.
5. The platform board removes the SoC Core well and VDDQ voltages in the following
sequence:
a. Power to the board SDRAM components.
b. V3P3S
c. V1P8S
d. VCC
a. Power to the board SDRAM components.
b. V3P3S
c. V1P8S
d. VCC
— Optionally, VCC may power-down the same time as VNN shown in step g below.
e. V1P0S
f.
f.
V1P35S
— V1P35S must power down before VNN or both rails (V1P35S and VNN) can be
power down simultaneously
g. VNN
h. VCCSRAM
h. VCCSRAM