Intel C2518 FH8065501516710 Data Sheet

Product codes

FH8065501516710

Intel

Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

173

Volume 2—System Address Maps—C2000 Product Family

Physical Address Space Map

10.1.1.1

Low MMIO

The Low MMIO range is shown in

Figure 10-2

By default, the CPU core memory reads targeting the Boot Vector range (FFFF_0000h-

FFFF_FFFFh) in Low MMIO are sent to the Boot Flash device connected to the platform

control unit. Memory write accesses to this area target DRAM. This allows the bootstrap

CPU core to fetch boot code from the Boot Flash from either the SoC SPI or LPC

interface, and then shadow that code to DRAM. For increased performance, the boot

code chooses to reroute read accesses targeting the boot vector range to access DRAM

using the BMBOUND.SEND_BOOT_VECTOR_TO_DRAM field. This allows execution of

the shadowed boot code from DRAM.

Note:

The 16MB BIOS Decode MMIO space under the Boot Vector range is enabled by default

via the BDE (BIOS Decode Enable (BDE) register is located in the configuration space at

bus 0, device 31 (decimal), function 0, at offset D8h). The BIOS Decode MMIO space

allows MMIO accesses to be sent to the LPC bridge or the SPI controller which is

determined by the boot selection strap pin FLEX_CLK_SE0.

Figure 10-2. Physical Address Space - Low MMIO

Low DRAM

DOS DRAM

High MMIO

Low MMIO

4 GB

64 GB

1 MB

Physical Address

Space

High DRAM

BMBOUND

Boot Vector

Abort Page

MMIO with Fixed

Memory Addresses

MMIO with variable

Memory Addresses

using Base Address

Register (BAR)

For details, refer to

tables in this chapter

256-MB ECAM location

determined by BECREG

PCI ECAM