Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

175

The DOS DRAM is the memory space, below 1 MB. In general, accesses from a 

processor targeting DOS DRAM target system DRAM. Exceptions are shown in 

Processor writes to the 64 KB (each) PROM ‘E’ and ‘F’ segments (000E_0000h-

000E_FFFFh and 000F_000h-000F_FFFFh) always target DRAM. The 

 register 

directs CPU core reads in these two segments to DRAM or to the I/O fabric (MMIO for 

the BIOS Decode Enable registers BDE.LEE and BDE.LFE). While accessible to the 

processor cores, these memory-mapped areas are not accessible to requestors which 

are PCI Express integrated endpoints, integrated root ports, or the endpoints of the 

root ports.

The BIOS Decode Enable (BDE) register is located in the configuration space at bus 0, 

device 31 (decimal), function 0, at offset D8h. This register enables decoding of the E 

and F segments of memory space and for various other small-address ranges.

The CPU core accesses to the 128 KB VGA/CSEG range (000A_0000h-000B_FFFFh) 

The SoC does not support the ISA Expansion ROM region (000C_0000h-

000D_FFFFh). This area always maps to system DRAM. Access is from the CPU only, no 

inbound access support. If for some reason an inbound access does occur, this access is 

aborted.

Low DRAM

High MMIO

Low MMIO

High DRAM

BMBOUND

(F0000h to FFFFFh)

(E0000h to EFFFFh)

(A0000h to BFFFFh)