Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

198

Order Number: 330061-002US

After the Soft Strap settings are applied (Soft Strap GBE_ALL_DISABLE must be “0” to 

get to this point) and after the integrated PCI devices exit the reset state, the 

information in the EEPROM is used to setup the configuration registers accessed during 

PCI enumeration. The EEPROM has the following control bits in the 

 words. There is one word for each of the four LAN Ports at EEPROM LAN-

word offset 20h:

• LAN_DIS
• LAN_PCI_DIS

If the LAN Port is enabled by its Soft Strap setting, the LAN_DIS and LAN_PCI_DIS 

settings in EEPROM are applied to LAN Ports 1, 2, and 3. A Soft-Strap enabled LAN Port 

0 cannot be disabled by its LAN_DIS and LAN_PCI_DIS bits in EEPROM. LAN Ports 1, 2, 

and 3 and associated PCI functions both enabled unless:

LAN_DIS = 1: The LAN is disabled. Here both PCIe function and LAN access for 

manageability are disabled.
LAN_PCI_DIS = 1: The associated LAN PCI function is disabled and is not 

enumerated and thus not connected to the host as an integrated PCIe 

endpoint. Even so, the LAN Port’s MAC is kept active and fully functional for 

manageability purposes and for BMC pass-through traffic.

The SoC BIOS can disable the integrated GbE controller PCI functions. The memory-

mapped Function Disable (FUNC_DIS) register of the Power Management Controller 

(PMC) portion of the SoC Platform Controller Unit (PCU) contains four bits to disable the 

four PCI functions.

The LAN Ports 0, 1, 2, and 3 are mapped to the four PCI functions 0, 1, 2, and 3 

respectively. There are no other mapping options supported by the SoC.