Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

199

The GbE controller LAN Port interface provides a complete CSMA/CD function 

supporting IEEE* 802.3 1000BASE-KX and 2500BASE-X (2.5 GbE) implementations. 

The controller also supports external PHY components that comply with the Serial 

Gigabit Media Independent Interface (SGMII). Refer to Appendix D of the Intel

Atom™ Processor C2000 Product Family Platform Design Guide (PDG) for guidance on 

which PHYs are supported.

The LAN Ports, each with its own MAC and set of transmit and receive queues, performs 

all of the functions required for transmission, reception, and collision handling called 

out in the standards.

Each LAN Port MAC can each be configured to use a different media interface. Selection 

of the media interface is programmable the 2-bit LINK_MODE field (bits 22, 23) of the 

MAC Extended Device Control (CTRL_EXT) register, located at offset 18h of the MMIO of 

the PCI function mapped to the LAN Port. The default link mode is set via the 2-bit Link 

, located at 16-bit word offset 24h of 

the particular LAN-Port base address of the EEPROM. The link modes are shown in 

.

The internal MAC and PCS supports 10/100/1000/2500 Mb/s operation. With SGMII 

link mode, both half- and full-duplex operation are supported at 10/100 Mb/s and only 

full-duplex operation at other SGMII speeds. With 1000BASE-KX or 2500BASE-KX link 

mode, only full-duplex operation is supported.

The 1000BASE-KX (1 Gb/s) and 2500BASE-X (2.5 Gb/s) link mode is used for Ethernet-

over-backplane implementations. In this mode, only parallel detection is supported and 

the LAN Port does not support the full Auto-Negotiation for Backplane Ethernet protocol 

as defined in IEEE Standard 802.3-2008 Clause 73, Auto-Negotiation for Backplane 

Ethernet.

The 2500BASE-X link mode is a special, enhanced speed mode of the 1000BASE-X link 

mode. The SoC has a pin strap to allow 2500BASE-X operation (see 

) and the GbE reference clock of the SoC must be driven with 

a 125-MHz differential signal instead of a 100-MHz signal (see 

). Also, the appropriate PCI Device ID (see 

) must be set for the PCI function 

mapped to the LAN Port.

00

01

1

1. The MAC for each LAN Port functions as 1 GbE with a 100-MHz reference clock or 2.5 GbE with a 125-MHz

reference clock.

1000BASE-KX (1 GbE)
2500BASE-X (2.5 GbE)

10

SGMII

11