Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

208

Order Number: 330061-002US

The NC-SI is an optional connection to an external BMC defined by the Distributed 

Management Task Force (DMTF) protocol defined in the Network Controller Sideband 

Interface (NC-SI) Specification (DSP0222). The It operates as a single interface with an 

external BMC, where all traffic between the GbE controller and the BMC flows through 

the interface. The GbE controller interface supports the standard DMTF NC-SI protocol 

and supports both pass-through traffic between the BMC and integrated GbE controller 

LAN functions as well as configuration traffic between the BMC and other SoC internal 

units as outlined in the Intel

Controller Programmer’s Reference Manual (PRM).

The NC-SI Specification describes a 50-MHz clock REF_CLK that is used by all the NC-SI 

devices. This clock must be provided by the platform board or one of the NC-SI 

devices. As an option the SoC integrated GbE controller can provide this 50-MHz 

REF_CLK. The internal circuitry of the SoC calls this signal NCSI_CLK_OUT which is 

internally connected to the NCSI_CLK_IN signal pin P50. The 

 register 

in EEPROM at 16-bit word location 21h, contains the NC-SI Output Clock Disable (bit 

13). When this bit is 0, the GbE controller drives the 50-MHz NC-SI REF_CLK 

(NCSI_CLK_OUT) via pin P50. When this bit is 1, the GbE controller does not drive the 

NC-SI clock and pin P50 is an input, NCSI_CLK_IN. The default setting of bit 13 is 0. If 

this bit is 0 (NCSI_CLK_OUT enabled), the Power Down Enable (bit 15) of 

 in EEPROM word 1Eh must also be 0 (its default setting).

If the GbE Controller is configured to provide the 50-MHz NC-SI clock signal to the rest 

of the platform board, then the SoC Soft Strap GBE_ALL_Disable must be a “0” (device 

is enabled).

If NC-SI is not used, then 

 register bit 13 must be set 

(NCSI_CLK_OUT disabled).

 register bits 15 and 14 control the drive strength of the GbE 

controller’s NC-SI Clock (NCSI_CLK_OUT) Pad Drive Strength and NC-SI Data 

(NCSI_CRS_DV and NCSI_RXD[1:0]) Pad Drive Strength respectively.

The Multi-Drop NC-SI (bit 11) of the Common Firmware Parameters 2 located in the 

Firmware section of the EEPROM defines the NC-SI topology as Point-to-Point (bit 11 = 

1) or Multi-Drop (bit 11 = 0, the default setting).

The GbE controller dynamically drives its NCSI_CRS_DV and NCSI_RXD[1:0] output 

signals as required by the sideband protocol:

• On power-up, the SoC floats the NC-SI outputs except for NCSI_CLK_OUT.
• If the GbE controller operates in Point-to-Point topology mode, it starts driving the 

NC-SI outputs some time following power-up.

• If the GbE controller operates in a Multi-Drop topology mode, it drives the NC-SI 

outputs as configured by the BMC.

Additional information is available in the Intel

Integrated GbE Controller Programmer’s Reference Manual (PRM).

Electrical and timing specifications are in 

.

Board design guidelines for both SMBus and NC-SI are given in the Intel

Processor C2000 Product Family Platform Design Guide (PDG).