Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

222

Order Number: 330061-002US

The SoC supports up to four PCI Express* Gen2 Root Port (RP) controllers. These are 

discovered by the software in the configuration space on bus 0, devices 1 through 4, 

each with one function (0). Some product SKUs have only one RP controller.

Each RP controller has three regions in Configuration Space. The contents of these 

regions and their offset values are:

1. PCI Standard Header

— Type 1 = PCI-to-PCI bridge

2. PCI Capabilities List

— PCI Power Management - Capability ID = 01h
— Message Signaled Interrupts (MSI) - Capability ID = 05h
— PCI Bridge Subsystem Vendor ID - Capability ID = 0Dh
— PCI Express - Capability ID = 10h
— Various implementation-specific and Intel-reserved registers

3. PCI Express Extended Capabilities List

— Advanced Error Reporting (AER) - Extended Capability ID = 0001h
— Access Control Services (ACS) - Extended Capability ID = 000Dh
— Various Vendor-Specific capabilities - Extended Capability ID = 000Bh

The vendor-specific extended capabilities in Configuration Space are primarily for Intel 

debug and testing purposes.

The SoC supports Peer-to-Peer (P2P) transactions among PCIe* Root Ports and 

between root ports and the integrated endpoints. This is governed by the 4 bits in the 

RTF Local (RTFL) register in the configuration space.

• Peer-to-Peer Enable for Root Port 1 (P2PEN_RP1)
• Peer-to-Peer Enable for Root Port 2 (P2PEN_RP2)
• Peer-to-Peer Enable for Root Port 3 (P2PEN_RP3)
• Peer-to-Peer Enable for Root Port 4 (P2PEN_RP4)

P2P memory read and memory write transactions are supported. The four P2P enable 

bits enable/disable this support. As an example, when the enable bit P2PEN_RP1 is 

programmed as 0, the P2P memory-mapped requests from Root Port 1 that target 

other peer agents (the other root ports, Root Complex integrated Endpoints, etc.) are 

disallowed. The SoC Fabric does master-abort these.

When the bit is programmed to a 1, peer-to-peer memory-mapped requests from Root 

Port 1 are allowed.

This field is locked by the Personality Lock Key Control Register (PLKCTL) register 

located in the fabric.

Other than the PCIe Root Ports, the SoC does not support complete peer-decode. An 

upstream request from a legacy block controller or a low pin count bus device does not 

target anything other than DDR3 system memory. The SoC does not decode memory or 

I/O accesses and redirect them.