Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

234

Order Number: 330061-002US

Each of the four PCI Express Root Port (RP) controllers is enabled for customer use 

based on the product SKU tables. A customer-programmable soft strap for each of the 

enabled RP controllers can be used to further disable RP controller(s). Before the BIOS 

boot process, the soft strap information (disable) is applied to each RP controller. Refer 

to Intel

Users Guide - Doc# 519715.

The 32-bit Root Port Bifurcation Control Register (RP_BIFCTL) in configuration space at 

bus 0, device 15, function 0, offset 0x40C, provides bifurcation control. The 3-bit 

Bifurcation Control 0 (BIFCTL0) field of this register can be set to one of five lane 

arrangements. Bit 16 of this register is the Link Train 0 (LINKTRN0) field which enables 

link training and bifurcation using values programmed in BIFCTL0. A value of 1 initiates 

link training. LINKTRN0 must not assert until after BIFCTL0 is programmed.

The control registers are decoded as shown in 

.

A write of 1 to the LINKTRN0 bit locks the setting of the BIFCTL0 register field as the 

port bifurcation control status information.

000

x4 x4 x4 x4

Lanes 15:12 support x4 in RP4

Lanes 11:8 support x4 in RP3

Lanes 7:4 support x4 in RP2

Lanes 3:0 support x4 in RP1

001

x4 x4 x8

Lanes 15:12 support x4 in RP4

Lanes 11:8 support x4 in RP3

(RP2 is unavailable)

Lanes 7:0 support x8 in RP1 

010

x8 x4 x4

(RP4 is unavailable)

Lanes 15:8 support x8 in RP3

Lanes 7:4 support x4 in RP2

Lanes 3:0 support x4 in RP1

011

x8 x8

(RP4 and PR2 are unavailable)

Lanes 15:8 support x8 in RP3

Lanes 7:0 support x8 in RP1

100

x16

(RP4, RP3, RP2 are unavailable)

Lanes 15:0 support x16 in RP1

101 - 111

Reserved