Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

235

After writing this bit to a 1, the software polls the Data Link Layer Link Active (DLLLA) 

bit in the Link Status Register (LINKSTS) register to determine if a port is up and 

running. The root ports do not automatically initiate link training after reset unless 

soft strap default values have already set this bit to 1. A write of 0 has no effect. A 

write of 1 locks this register bit and initiates link training.

The link widths in degraded mode are shown in 

.

In general, most designers want to achieve a single platform design that can be applied 

to different SoC SKUs. Sometimes it is difficult to implement all feature sets from 

different SKUs into a single design. Designers need to make a balanced decision about 

what is important for their design. This section provides design considerations for the 

PCI Express* configuration support with various SoC SKUs.

1. This is the native width link that is running at the time the degraded-mode operation kicks-in.

X16

x8 on either lanes 0-7, or 8-15

x4 on either lanes 0-3, or 12-15

x2 on either lanes 0-1, or 14-15

x1 on either lane 0 or 15

X8

Assuming 2 cards present in the system

x4 on either lanes 0-3, 4-7, 8-11 or 12-15

x2 on either lanes 0-1, 6-7, 8-9, or 14-15

x1 on either lane 0, 7, 8, or 15

X4

Assuming 4 cards present in the system

x2 on either lanes 0-1, 2-3, 4-5, 6-7, 8-9, 10-11, 12-13, or 14-15

x1 on either lane 0, 3, 4, 7, 8, 11, 12, or 15