Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

249

The SoC contains a set of registers that shadow the contents of the legacy IDE 

registers. The behavior of the Command and Control Block registers, PIO, and DMA 

data transfers, resets, and interrupts are all emulated.

The SoC asserts INTR when the master device completes the EDD command regardless 

of the command completion status of the slave device. If the master completes EDD 

first, an INTR is generated and BSY remains 1 until the slave completes the command. 

If the slave completes EDD first, BSY is 0 when the master completes the EDD 

command and asserts INTR. The software must wait for busy to clear (0) before 

completing an EDD command, as required by the ATA5 through ATA7 (T13) industry 

standards.

The SATA host controller supports 48-bit LBA through the host-to-device register FIS 

when accesses are performed using writes to the task file. The SATA host controller 

ensures that the correct data is put into the correct byte of the host-to-device FIS. 

Special considerations exist when reading from the task file to support 48-bit LBA 

operation. The software may need to read all 16 bits. Since the registers are only 8-bits 

wide and act as a FIFO, a bit must be set in the device/control register, which is at 

offset 3F6h for primary and 376h for secondary (or their native counterparts).

If the software clears bit 7 of the control register before performing a read, the last 

item written is returned from the FIFO. If the software sets bit 7 of the control register 

before performing a read, the first item written is returned from the FIFO.

The SoC provides for basic SATA swap bay support using the PSC register configuration 

bits and power management flows. A device is powered down by the software and the 

port is then disabled, allowing removal and insertion of a new device.

This SATA swap bay operation requires board hardware (implementation specific), 

BIOS, and operating system support.