Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

309

2

31:0

DPTR

 Byte-aligned pointer to the starting location of the data 

buffer. 
The hardware reads from memory and transmit exactly as many bytes as is 

indicated by WRLNTH field. This does not include the address fields of the 

message (i.e., Start Address/Repeated Start Address) and byte count if any. 
The hardware is expected to write to memory exactly as many bytes as is 

indicated by the RDLNTH field (unless an error condition exists and the target 

fails to provide the expected number of bytes, in which case the appropriate 

error bits are set).

3

63:32

DPTR

1. The SMBus Specification is vague about the condition of the CRC error when the master is initiating a READ

and the target provides the CRC. Irrespective of the fact that the CRC is correct or incorrect, the master must

NACK the cycle and assert STOP. The SMT hardware informs the firmware of the incorrectness of the received

CRC and leaves it up to the firmware for further action. See the System Management Bus (SMBus)

, Version 2.0, page 27, paragraph 3.