Intel C2518 FH8065501516710 Data Sheet
Product codes
FH8065501516710
Volume 2—SMBus 2.0 Unit 1 - Host—C2000 Product Family
Controller Characteristics and Operation
Intel
®
Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
310
Order Number: 330061-002US
15.4.7.3
Master Descriptor Usage
Descriptors are used for SMT transactions are initiated by the firmware. The hardware
decodes the I
2
C, PEC, WRLNTH, and RDLNTH fields to differentiate between types of
and I
2
).
The master transaction flow is defined in
The master retry flow is defined in
15.4.7.3.1
SMBus Protocol Transfers
Table 15-14
illustrates how the hardware uses the control information in the descriptor.
Note:
1. The firmware must ensure that I
2
C bit is 0 when initiating SMBus transactions.
2. Target Address and R/W# indication is taken from the descriptor.
3. PEC-enabled write transactions proceed in the same manner except that the
3. PEC-enabled write transactions proceed in the same manner except that the
hardware appends PEC after the last data phase.
4. PEC-enabled read transactions instruct the hardware to check CRC and report
status to the firmware.
Note:
See
for restrictions on writes to certain addresses.
Table 15-14. SMBus Transaction Encodings (Sheet 1 of 2)
SMBus
Command
BLK
C/
WRL
WRLNTH
RDLNTH
RW
(0=W;
1=R)
DPTR
(Points to TX
Data)
DPTR
(Points to RX
Data)
Quick
Command
0
0
0
0
Read/
Write
X
X
Send Byte
0
1
Command
0
0
X
X
Receive
Byte
0
0
0
1
1
X
Valid and points to
a buffer where the
received byte is
placed.
Write Byte
0
0
2
0
0
Valid and points to
2 bytes (command
and 1-data byte).
X
Write Word
0
0
3
0
0
Valid and points to
3 bytes (command
and 2-data bytes).
X
Read Byte
0
1
Command
1
1
X
Valid and points to
a buffer where the
received byte is
placed.
Read Word
0
1
Command
2
1
X
Valid and points to
a buffer where the
received 2 bytes
are placed.
Process Call
0
0
3
2
0
Valid and points to
3 bytes (command
and 2-data bytes).
Valid and points to
a buffer where the
received 2 bytes
are placed.