Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

318

Order Number: 330061-002US

The hardware contains separate timers and counters to auto-retry unsuccessful SMBus 

cycles that it masters on SMBus.

Two counters for Time Between Retries and Retries Due To Collision are on the bus. Any 

failed cycle due to collision first exhausts the collision counter before decrementing the 

retry counter. The Time Between Retries is maintained only between two successive 

transaction retries and not between two successive retries due to collision.

The high-level flow in pseudo code is:

//Master Transaction begin

MASTER_FLOW

// All registers are defined in RPOLICY register

RELOAD RETRY

// Collision retries

COLRTRY

// Time between retries

TBR

While (RETRY >= 0) {

RELOAD TBR

RELOAD COLRTRY

Send Cycle on SMBus

While (SMBus COLLISION & (COLRTRY > 0)) {

COLRTRY = COLRTRY - 1

WAIT for SMBus IDLE

Send Cycle on SMBus

} 

If (SMBus ACK) {

Update Status in descriptor and WB to memory

Send Interrupt if enabled

GOTO MASTERFLOW and wait for new cycle

BREAK

} else if

(((RETRY == 0) & SMBus NACK) || SMBus Timeout) {

Update Status in descriptor and WB to memory

Set Master Error and send MSI (if enabled) after updating SMTICL

Clear DMA Start/Stop Bit

GOTO MASTERFLOW and wait for FW to set Start bit

BREAK

} else if (SMBus NACK & (RETRY > 0)){

RETRY = RETRY - 1

CNTDOWN TBR

WAIT for TBR to expire

}

}