Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

327

As described in the target descriptor section, a ring buffer is maintained by the 

firmware where the hardware sends the notifications to the firmware. The various 

notifications are:

1. External master initiates a read: notification of success/failure is sent to the 

firmware in header. Read data is returned by the hardware (data is pre-

programmed by the firmware).

2. External master initiates a write: notification of success/failure is sent to the 

firmware in header. Write data received by the hardware is sent as payload to 

memory.

1. Target buffer is empty when HWtHeadPtr = FWtTailPtr (HTHP = FTTP).
2. Target buffer is full when (HTHP = FTTP - 4B) or (HTHP - FTTP = TBS).
3. Buffer wrap for HTHP is when HTHP = TBS. When this exists, the hardware writes 

Dword to memory and then roll over to 0x0000 unless buffer full condition exists, 

i.e., FTTP = 0x0000.

4. The firmware must never increment the FWtTailPtr to a value greater than the 

HWtHeadPtr.

5. If the target ring buffer is N-bytes deep, only N-1 bytes are utilized since the 

hardware/firmware do not implement a wrap bit.

1. The firmware allocates a buffer in the firmware memory to be used as the target 

ring buffer as one contiguous space.

2. The firmware then programs up the Target Buffer Base Address (TBBA) register 

with a 64B aligned memory address of the ring buffer.

3. The firmware assigns the Target Buffer Size (TBS) register with the actual size of 

the ring buffer with the maximum limit of 64 KB.

4. The hardware reset initializes the HWtHeadPtr and FWtTailPtr to 0.
5. The firmware enables all target addresses as needed, and program the register-

based read data as needed.

6. The firmware also programs interrupts as needed.
7. Finally the firmware sets the TPOLICY.TGTEN bit to enable the target logic.