Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

341

SMT hardware has the following causes of interrupts (if enabled).

1. Master Interrupt - The hardware generates master interrupts for transactions 

ending successfully or in failure.

2. Target Interrupt - Generated whenever the hardware writes data and/or the header 

to memory.

3. Error Interrupt - Generated whenever the hardware detects a bus error or a 

resources error.

First-error cause information is logged in ERRINFO. Also, error interrupts also support 

masking of escalation to Advanced Error Reporting (AER); see ERRAERMSK.

ERRINTMSK.IMAE: this bit is assumed to be 1 when MSICTL.MSIE is set. IMAE occurs 

only if PCICMD.BME is clear and MSI requires BME to be set.

Master Descriptor INT 

field

MSTS.MIS

Successful completion of master cycles

MSTS.MEIE

MSTS.MEIS

Unsuccessful completion of master cycles

TCTRL.TIE

TSTS.TIS

TCTRL.SCHWBP
TCTRL.UCHWBP
TCTRL.URxTWP

Successful completion of target cycles
Unsuccessful completion of target cycles
Unsuccessful completion of write to target

ERRINTMSK.CKLTO

ERRSTS.CKLTO

SMBus clock-low time-out

ERRINTMSK.TRBF

ERRSTS.TRBF

Target ring buffer is full

ERRINTMSK.TRBAF

ERRSTS.TRBAF

Target ring buffer is almost full

ERRINTMSK.IHIE

ERRSTS.IHIE

Read completion with non-successful 

status

ERRINTMSK.IMAE

ERRSTS.IMAE

Request is made when PCICMD.BME is 

clear

ERRINTMSK.ITE

ERRSTS.ITE

Error in IPI transmit transaction

ERRINTMSK.IRDPE

ERRSTS.IRDPE

Data parity error in IPI receive transaction

ERRINTMSK.IRE

ERRSTS.IRE

Error in IPI receive transaction

ERRINTMSK.SPDWE

ERRSTS.SPDWE

MCTRL.SPDDIS

Write is attempted to SPD address range

ERRINTMSK.CPE

ERRSTS.CPE

CSR parity error