Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

342

Order Number: 330061-002US

Two causes for a master interrupt are:

1. Successful - The Interrupt bit in the descriptor is set to indicate the hardware must 

generate an interrupt on successful completion of the descriptor. An Interrupt 

Status Register bit is defined in the MMIO space (MSTS.MIS), which is set every 

time the hardware retires a descriptor. The enable for this interrupt is defined 

within each individual descriptor.

2. Failure - The descriptor is not successfully completed due to an SMBus error. This 

interrupt has a Cause Enable (MCTRL.MEIE) and a Cause Status bit (MSTS.MEIS) in 

the device MMIO space.

Upon completion of descriptor processing, either MSTS.MIS (successful completion) or 

MSTS.MEIS (unsuccessful completion) must be set by the hardware. This distinction is 

required so that if the firmware disables MSI (i.e., chooses to operate in polling mode) 

by polling both flags, it determines when the descriptor has completed and its 

completion status.

The master interrupts are sent for descriptor-based transactions. Therefore, they are 

serialized and ordered with respect to the descriptor writeback and specifically tied to 

the descriptor just processed due to operand requirement.

1. Run descriptor-based master transaction on SMBus.
2. Perform Descriptor Status WB to memory. (See Status WB field in 

, 

3. Write 1 to the appropriate Cause Status bit (MCTRL.MEIS or MSTS.MIS).
4. If that appropriate interrupt is enabled (locally and globally), MSI is sent and the 

cause status is auto-cleared, else MSI is not sent and the cause remains set and 

the firmware is expected to poll the response.

MSTS.MEIS itself merely indicates an unsuccessful completion. The descriptor Status 

WB field contains full details of transaction and error conditions.

Firmware implementation:

1. If the cause is set for a previous descriptor-based transaction and the firmware 

enables the global (and local) interrupt enable, the hardware does not send an 

interrupt for a previously set cause.

2. It is the responsibility of the firmware to ensure that if the cause is set, the 

previous transactions are accounted for before enabling the MSI (globally and 

locally)