Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

356

Order Number: 330061-002US

The features of the key PCU blocks are:

• Intel  Legacy  Block  (iLB)

— Discovered by the software at bus 0, device 31 (decimal), function 0 in the 

configuration address space

— Supports legacy PC platform features
— Sub-blocks include LPC, General Purpose I/O (GPIO), 8259 PIC, IOxAPIC, 8254 

timers, HPET timers and the RTC

• SMBus Host Controller

— Discovered by the software at bus 0, device 31 (decimal), function 3 in the 

configuration address space

— Supports System Management Bus (SMBus) 2.0 Specification
— No support for SMBus slave functionality aside from the Host Notify command
— No Total Cost of Ownership (TCO) feature support

• Universal Asynchronous Receiver/Transmitter (UART)

— Two UART interfaces available: UART0 (COM1) and UART1 (COM2)
— 16550 controller compliant
— Reduced signal count: TX and RX only
— COM1 interface using eight I/O addressed mapped registers (0x3F8-0x3FF)
— COM2 interface using eight I/O addressed mapped registers (0x2F8-0x2FF)

• Serial Peripheral Interface (SPI)

— Uses memory-mapped I/O. The base address is in the iLB Configuration 

registers.

— For one or two SPI Flash, of up to 16-MB size each, only. No other SPI 

peripherals are supported.

— Stores the boot firmware and system configuration data
— Supports frequencies of 20 MHz (default) and 33 MHz

• Power Management Controller (PMC)

— Uses the memory-mapped I/O. The base address is in the iLB Configuration 

registers.

— Uses the I/O-space-mapped I/O. The base address is in the iLB Configuration 

registers.

— Controls many of the power management and reset features present in the SoC