Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

357

Strapping is a hardware mechanism used for system configuration control. Some of the 

functional signal pins are also defined as SoC strapping pins. These pins are sampled at 

various reset points to select configuration information. Each strapping pin is briefly re-

configured as an SoC input, and its state is sampled and latched by the SoC hardware. 

After sampling, the SoC pin is configured in its normal functional characteristics.

The strapping pins are listed in 

.

AL63

Reserved for Intel.

Must be logic low during sampling.

20 kΩ

Pull-down

1

AL62

Reserved for Intel.

Must be logic low during sampling.

20 kΩ

Pull-down

1

AL65

Reserved for Intel.

Must be logic low during sampling.

20 kΩ

Pull-down

1

AH50

SPI Flash Descriptor security is overridden when the 

strap pin is sampled low.
This pin is temporarily pulled-up internally during the 

sample period.

20 kΩ

Pull-up

1

AH59

Boot Flash device location. LPC bus interface (if sensed 

low) versus SPI (sensed high).
This pin is temporarily pulled-up internally during the 

sample period.

20 kΩ

Pull-up

1

AG56

This pin is temporarily pulled-up internally during the 

sample period.
Must be logic high during sampling.

20 kΩ

Pull-up

1

AR51

Reserved for Intel.

20 kΩ

Pull-up

1

V66

Reserved for Intel.

Must be logic low during sampling.

SUS Power OK

20 kΩ

Pull-down

1

W54

If sensed low, the 2.5-GbE capability, if available, is 

disabled. This pin must be sampled high for the 

2.5-GbE capability to function.
This pin is temporarily pulled-down internally during 

the sample period.

SUS Power OK

20 kΩ

Pull-down

2

T53

Reserved for Intel.

SUS Power OK

None

1

Y63

Reserved for Intel.

SUS Power OK

None

1

AD58

Reserved for Intel.

Must be logic low during sampling.

SUS Power OK

20 kΩ

Pull-down

1

AE62

Reserved for Intel.

Must be logic low during sampling.

SUS Power OK

20 kΩ

Pull-down

1

AB65

Reserved for Intel.

Must be logic low during sampling.

SUS Power OK

20 kΩ

Pull-down

1

Y65

After G3 Enable (AG3E) strap. This strap is used for 

the first G3 boot.
If sensed low, the system transitions to the S0 state 

(boot) when power is applied.
If sensed high, the system transitions to the S5 state 

(Soft Off) when power is applied. In the S5 state, the 

only enabled wake-up event is the power button 

(PMU_PWRBTN_B) or any enabled wake event that 

was preserved through a power failure.

SUS Power OK

20 kΩ

Pull-up

1