Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

359

For the hard strap pins, the customer board may need to provide external pull-down 

and pull-up resistors to force the pin to the intended state of the strapping mechanism.

The pins sampled by 

 is asserted. Before 

and during the assertion, these pins are temporarily SoC input pins and, if indicated, 

have an internal temporary termination resistor applied only during the sampling 

period. The hard pin-strap information must be held valid at the SoC inputs for a 

minimum of 400 ns after COREPWROK is asserted.

• Core-Well Strap-pin hold time required after COREPOWER driven high = 400 ns 

minimum

• SUS-Well Strap-pin hold time required after RSMRST_B (active low) driven 

high = 400 ns minimum

All of these hard strap pins return to their native, functional signal characteristics after 

the sampling period.

The strapping pins marked as Reserved for Intel do not need any special attention from 

the board designer for proper operation as long as the internal pull-up/pull-down is not 

defeated by the platform board design during the sampling period.

These board settings of the strapping mechanism are overwritten by the DFX Tap of the 

SoC. The Intel debug and test software reads and retains the board settings before the 

DFX Tap overwrite.