Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

362

Order Number: 330061-002US

The following section provides details related to the storage and configuration of soft 

straps which are used to determine the native function for each specific capability.

Soft strap information is stored within the Flash Descriptor region 0 of the SPI firmware 

image. The start address of the soft strap definition space is located within the Flash 

Map 1 register within the Flash Strap Base Address Register (FLMAP1[23:16]) field 

referred to as FISBA. See 

The default value represents the internal strap signal value used if the SPI Flash is not 

valid. 

At boot, the SPI controller reads the soft strap content from the SPI Flash and then 

provides this soft strap content to the various SoC controllers.

0

+ 0h

1:0

BBS

SPI Boot Block Size:
2'b00: 64 KB (Default)
2'b01: 128 KB
2'b10: 256 KB
2'b11: Reserved

2'b00

0

+ 0h

2

Intel

®

 QuickAssist 

Technology

Disable (SKU 

Specific)

Intel

®

 QuickAssist Technology (B0:D11) Disable:

1'b0 (false) - Enable
1'b1 (true) - Disable

Has no effect if the SKU does not have Intel

®

 

QuickAssist Technology

1'b0

0

+ 0h

3

SATA 3

Disable

SATA 3 (B0:D24) Disable:
1'b0 (false) - Enable
1'b1 (true) - Disable

Ensure these soft straps are set to match this selection.

• SoC Strap 6 SATA 3 Power Enable Lane 0
• SoC Strap 6 SATA 3 Power Enable Lane 1
• SoC Strap 6 SATA 3 Power Enable

1'b0

0

+ 0h

4

Reserved

Reserved

1’b0

0

+ 0h

5

GbE Port 1

Disable

GbE Port 1 (B0:D20:F1) Disabled:
1'b0 (false) - Enable
1'b1 (true) - Disable

1'b0

0

+ 0h

6

GbE Port 2

Disable

GbE Port 2 (B0:D20:F2) Disabled:
1'b0 (false) - Enable
1'b1 (true) - Disable

1'b0

0

+ 0h

7

GbE Port 3

Disable

GbE Port 3 (B0:D20:F3) Disabled:
1'b0 (false) - Enable
1'b1 (true) - Disable

1'b0