Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

Datasheet, Vol. 2 of 3

September 2014

364

Order Number: 330061-002US

0

+ 0h

14

PCIe RP3

Disable

PCIe Root Port 3 (B0:D3) Disabled: 
1'b0 (false) - Enabled
1'b1 (true) - Disabled

If PCIe Root Port 3 is disabled, PCIe Root Port 4 must 

be disabled as well.

Ensure these soft straps are set to match this selection.

• SoC Strap 5 PCIe Lane Power Enable 8
• SoC Strap 5 PCIe Lane Power Enable 9
• SoC Strap 5 PCIe Lane Power Enable 10
• SoC Strap 5 PCIe Lane Power Enable 11
• SoC Strap 5 PCIe Lane Power Enable 12
• SoC Strap 5 PCIe Lane Power Enable 13
• SoC Strap 5 PCIe Lane Power Enable 14
• SoC Strap 5 PCIe Lane Power Enable 15

• SoC Strap 8 PCIe RP3 (B0:D3) Disable

1'b0

0

+ 0h

15

PCIe RP4

Disable

PCIe Root Port 4 (B0:D4) Disabled: 
1'b0 (false) - Enabled
1'b1 (true) - Disabled

Ensure these soft straps are set to match this selection.

• SoC Strap 5 PCIe Lane Power Enable 12
• SoC Strap 5 PCIe Lane Power Enable 13
• SoC Strap 5 PCIe Lane Power Enable 14
• SoC Strap 5 PCIe Lane Power Enable 15

• SoC Strap 8 PCIe RP4 (B0:D4) Disable

1'b0

0

+ 0H

16

Reserved

Reserved

1'b0

0

+ 0h

17

GbE Powered in S5

GbE functionality available in S5 system state:
1'b0 (false) - Not available
1'b1 (true) - Available

1'b0

0

+ 0h

19:18

Reserved

Reserved

3'b000

0

+ 0h

20

VDDQ Channel 0

Enable

Channel 0 DRAM SVID VDDQ Voltage Enabled
1'b0 (false) - Disabled (No SVID Support)
1'b1 (true) - Enabled (With SVID Support)

1. SVID based VR on VDDQ0 and SVID based VR on VDDQ1

• Soft straps should be set to VDDQ CH0 : 1 , VDDQ CH1 : 1

2. Single SVID Based VR for both VDDQ0 and VDDQ1:

• Soft straps should be set to VDDQ CH0 : 1 , VDDQ CH1 : 0

3. No SVID based VR for both VDDQ0 and VDDQ1:

• Soft straps should be set to VDDQ CH0 : 0 , VDDQ CH1 : 0

1'b1