Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

379

In the SoC, the communication between the SMBus controller and the internal PECI 

bridge utilizes the SMBus block write and block read transactions as defined in the 

SMBus 2.0 specifications.

See 

 to interpret the SMBus protocol drawing.

S

Start Condition 

Sr

Repeated Start Condition

Rd

Read (bit value of 1)

Wr

Write (bit value 0)

X

Shown under a field indicates that field is required 

To have the value of ‘x’

A 

Acknowledge (this bit position is 0 for an ACK or 1 for a NACK)

P Stop 

Condition

PEC 

Packet Error Code

…

Continuation of Protocol

Master to Slave

Slave to Master