Intel C2518 FH8065501516710 Data Sheet

Product codes
FH8065501516710
Page of 746
Volume 2—SMBus 2.0 Unit 0 - PCU—C2000 Product Family
Signal Descriptions
Intel
®
 Atom™ Processor C2000 Product Family for Microserver
Datasheet, Vol. 2 of 3
September 2014
430
Order Number: 330061-002US
18.1
Signal Descriptions
The signal description table has the following headings:
• Signal Name: The name of the signal/pin
• Direction: The buffer direction is either input, output, or I/O (bi-directional)
• Type: The buffer type
• Description: A brief explanation of the signal function
The optional SMBus 2.0 signal, SMBSUS#, is not supported.
18.2
General Architecture
At its network layer, the System Management Bus Specification refers to three types of 
devices:
• Slave Device - A device that is receiving or responding to a command.
• Master - A device that issues commands, generates the clocks, and terminates the 
transfer.
• Host - A specialized master that provides the main interface to the system CPU. A 
host must be a master-slave and must support the SMBus host notify protocol. At 
most, one host exists in a system.
The SMBus controller described in this chapter is a system host. It is an example of an 
SMBus device that acts as a host most of the time but that includes some slave-device 
behavior.
The programming model of the host controller is combined into two portions: a PCI 
configuration portion and a system I/O mapped portion. All static configurations, such 
as the I/O base address, is done using the PCI configuration space. Real-time 
programming of the host interface is done in the system I/O space.
The SMBus interface is disabled by setting FUNC_DIS_2.SMB_DIS to 1b.
Table 18-2. Signal Names
Signal Name
Direction
Type
Description
I/OD
I/OD
I/OD
SMBus Alert (SMBALERT#):
 This signal wakes the system or 
generates a System Management Interrupt (SMI).
This signal is muxed with GPIOS_10 and is used by other functions.