Intel C2518 FH8065501516710 Data Sheet

Intel

®

 Atom™ Processor C2000 Product Family for Microserver

September 2014

Datasheet, Vol. 2 of 3

Order Number: 330061-002US

447

The PMC provides the SoC with these features and functions:

• Power-up sequencing.
• Sleep-state sequencing.
• Global and host partition reset sequencing.
• Keeps the controller S0-state run-time code in integrated RAM.
• Provides SMI and SCI interface and sequencing with the CPU.
• Host TCO watchdog timer.
• Dynamic power management control.
• Lock mechanism for the integrated USB 2.0 ports.

Most of the PMC circuitry and registers are powered by the Suspend (SUS) power well. 

A small portion of its registers are in the RTC power well. The circuitry for the reset-

button input signal is in the core power well.

The SUS power well contains:

• Logic circuitry that is first to become active and powers-up the rest of the SUS well 

circuitry.

• The PMC microprocessor, its internal code ROM, RAM, and registers.
• Logic circuits that are needed during the sleep states.
• PMC registers accessed by the CPU in the I/O and memory space.
• Legacy CPU watchdog timers.

The RTC power well contains:

• Certain register bits.
• Logic circuitry to generate the power-OK signals.

The core power well contains:

• Reset button input.

The software interfaces with the PMC through a number of registers in the I/O and 

memory space.

Memory

9-bit BAR

512 bytes

Memory used by the PMC circuitry. The 

software configuration and status bits for 

power management and SMI control.

I/O

Fixed 16 bits

0x0092

1 byte

INIT control.

I/O

Fixed 16 bits

0x0CF9

1 byte

Host reset control.

I/O

7-bit BAR

96 bytes

ACPI registers for wake and SMI control.

16 bytes

TCO timer registers.